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*ECEN474/704: (Analog) VLSI Circuit Design Spring Mixed-Signal Center Texas AM University Lecture 6:...*

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Sam PalermoAnalog & Mixed-Signal Center

Texas A&M University

Lecture 6: Table-Based (gm/ID) Design

ECEN474/704: (Analog) VLSI Circuit Design Spring 2016

Announcements

HW1 is due today Exam1 is on Feb 24

9:10-10:35PM (10 extra minutes) Closed book w/ one standard note sheet 8.5x11 front & back Bring your calculator Covers material through lecture 5 Previous years exam 1s are posted on the website for reference

Reading gm/ID paper and book reference posted on website

Material is only supplementary reference Razavi Chapter 5

2

Agenda

Technology characterization for design Table-based (gm/ID) design example Adapted from Prof. B. Murmann (Stanford)

notes

3

How to Design with Modern Sub-Micron (Nanometer) Transistors? Hand calculations with square-law model can deviate

significantly from actual device performance However, advanced model equations are too tedious for design

Tempts designers to dive straight to simulation with little understanding on circuit performance trade-offs Spice Monkey approach

How can we accurately design when hand analysis models are way off?

Employ a design methodology which leverages characterization data from BSIM simulations

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The Problem

5

[Murmann]

The Solution

6

[Murmann]

Technology Characterization for Design

Generate data for the following over a reasonable range of gm/ID and channel lengths Transit frequency (fT) Intrinsic gain (gm/gds) Current density (ID/W)

Also useful is extrinsic capacitor ratios Cgd/Cgg and Cdd/Cgg

Parameters are (to first order) independent of transistor width, which enables normalized design

Do design hand calculations using the generated technology data

Still need to understand how the circuit operates for an efficient design!!!

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gm/ID

8

These plots tell us how much transconductance (gm) we can get for a given current (ID)

The transistor is a more efficient transconductor at low overdrive voltages

A main trade-off will be the transistor frequency response (fT)

We will use gm/ID as the reference axis to compare other transistor parameters

Intrinsic Transistor Gain (gm/go)

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These plots tell us how much intrinsic transistor gain we have The transistor has higher intrinsic gain at lower overdrive values due to the

output resistance decreasing faster than the transconductance increases at higher current levels

Plotted vs gm/ID shows that a after a certain minimum level, the transistor gain is somewhat flat

Transit Frequency, fT

10

ggm

GDGS

mT C

gCC

gf 22

The transit frequency is defined as the frequency when the transistor small-signal current gain goes to unity with the source and drain at AC grounds

Overall, the ratio of gm to Cgg comes up often in analog circuits, and is a good metric to compare the device frequency response (speed)

Transistor fT increases with overdrive voltage and high fT values demand a low gm/ID If you need high bandwidth, you have to operate the device at low efficiency

Current Density, ID/W

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Ultimately, we need to know how to size our devices to get a certain current The current density of a transistor increases with increased VGS or overdrive

voltage High gm/ID requires low current density, which implies bigger devices for a

given current

CS Amplifier Design Example

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Specifications 0.6m technology |Av| 4V/V fu 100MHz CL = 5pF Vdd = 3V

CS Amplifier Small-Signal Model (No RS)

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Lo

Lo

dbgdL

mgd

i

o

RrRrR

RCCCsRgsC

vv

||

||

||

1 where ,

L

mpvu

Lmmv

LLdbgdLp

gd

mz

CgA

RgRgA

CRCCCR

Cg

||

||

11

)T frequency, high veryat (located

Design Procedure

1. Determine gm from design specificationsa. u in this example

2. Pick transistor La. Short channel high fT (high bandwidth)b. Long channel high ro (high gain)

3. Pick gm/ID (or fT)a. Large gm/ID low power, large signal swing (low Vov)b. Small gm/ID high fT (high speed)c. May also be set by common-mode considerations

4. Determine ID/W from ID/W vs gm/ID chart5. Determine W from ID/W

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Other approaches exist

1. Determine gm (& RL)

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From u and DC gain specification

dbgd C and C neglecting to due low slightly be may this Note,

VmApFMHzCgCgA

Lum

L

mpvu

/14.351002

kVmAg

AR

gAR

RgRgA

m

vL

m

vL

Lmmv

5.1/14.3

8.4

||

effects rfor compensate to margin 20% Adding o

2. Pick Transistor L

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Need to look at gain and fT plots

Since amplifier Av4, min channel length (L=0.6m) will work with gm/ID~>2 Min channel length provides highest fT at this gm/ID setting

3. Pick gm/ID (or fT)

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Setting ID for VO=1.5V for large output swing range

mAk

VVID 15.15.13

114.31

/14.3 VmA

VmAIg

D

m

Verify Transistor Gain & fT at gm/ID Setting

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Gain = 30.6 fT = 6.7GHz

Transistor gain=30.6 >> amplifier Av4 Transistor fT=6.7GHz >> amplifier fu=100MHz gm/ID setting is acceptable

4. Determine Current Density (ID/W)

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ID/W = 20.2

gm/ID=3.14V-1 maps to a current density of 20.2A/m

VGS=1.15V

Verify current density is achievable at a reasonable VGS

VGS=1.15V is reasonable with Vdd=3V & VDS=1.5V

For layout considerations and to comply with the technology design rules Adjust 49.5m to 49.2m and realize with 8

fingers of 6.15m This should match our predictions well, as the

charts are extracted with a 6m device Although it shouldnt be too sensitive to exact

finger width

From Step 3, we determined that ID=1mA

5. Determine Transistor W from ID/W

20

mmAmA

WIIW

D

D

5.49/2.20

1

Simulation Circuit

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Operating Point Information

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N0:betaeff 9.97E03N0:cbb 2.48E14N0:cbd 1.28E17N0:cbdbi 5.56E14N0:cbg 8.56E15N0:cbs 1.63E14N0:cbsbi 1.63E14N0:cdb 4.26E15N0:cdd 1.25E14N0:cddbi 5.56E14N0:cdg 2.87E14N0:cds 2.05E14N0:cgb 1.42E14N0:cgbovl 0N0:cgd 1.25E14N0:cgdbi 5.07E17N0:cgdovl 1.26E14N0:cgg 7.41E14N0:cggbi 4.90E14N0:cgs 4.74E14N0:cgsbi 3.49E14N0:cgsovl 1.26E14N0:cjd 5.56E14N0:cjs 0N0:csb 6.39E15N0:csd 2.60E17

N0:csg 3.68E14N0:css 4.32E14N0:cssbi 3.07E14N0:gbd 0N0:gbs 1.03E10N0:gds 1.02E04N0:gm 3.13E03N0:gmbs 7.64E04N0:gmoverid 3.131N0:i1 9.99E04N0:i3 9.99E04N0:i4 8.00E14N0:ibd 8.00E14N0:ibs 0N0:ibulk 8.00E14N0:id 9.99E04N0:ids 9.99E04N0:igb 0N0:igcd 0N0:igcs 0N0:igd 0N0:igidl 0N0:igisl 0N0:igs 0N0:is 9.99E04N0:isub 0N0:pwr 1.50E03

N0:qb 5.03E14N0:qbd 9.46E14N0:qbi 5.03E14N0:qbs 0N0:qd 3.72E15N0:qdi 8.10E15N0:qg 8.07E14N0:qgi 7.06E14N0:qinv 4.20E03N0:qsi 1.21E14N0:qsrco 2.66E14N0:region 2N0:reversed 0N0:ron 1.50E+03N0:type 0N0:vbs 0N0:vdb 1.502N0:vds 1.502N0:vdsat 3.91E01N0:vfbeff 9.65E01N0:vgb 1.153N0:vgd 3.49E01N0:vgs 1.153N0:vgsteff 5.00E01N0:vth 6.53E01

Design Value

1mA

3.14mA/V3.14V-1

Total Cgate = Cgg = 74.1fF

Total Cdrain = Cdd + Cjd = 12.5fF + 55.6fF = 68.1fF

Total Csource = Css + Cjs = 43.2fF + 0fF = 43.2fF

AC Response

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Av= 12.2dB = 4.07V/V

fu = 95.5MHz

Design is very close to specs Discrepancies come from neglecting ro and Cdrain With design table information we can include estimates of these in

our original procedure for more accurate results

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